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Description: 这是一段闹铃时钟的设计算法，可以实现定点报时，程序简单，异于读懂-This is a section of the alarm clock design algorithm can be designated timekeeping procedures, different from the read
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Size: 2697216 |
Author: 周明源 |
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Description: atmega16 实现闹钟，使用矩阵键盘，算法采用死循环-the atmega16 achieve alarm clock, the use of the keyboard matrix, the algorithm uses the infinite loop
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Size: 6144 |
Author: 林竹影 |
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Description: 包括了Clock,，FIFO，LRU，OPT，随机替换五种页面置换算法-Including the Clock, the FIFO, LRU, OPT, randomly replace the five page replacement algorithm
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Size: 955392 |
Author: joe |
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Description: 操作系统页面置换算法的源代码，分别包含最佳置换算法，先进先出置换算法，最近最久未使用置换算法以及简单的clock置换算法。-The source code of the operating system page replacement algorithm, respectively, contain the best replacement algorithm, FIFO replacement algorithm, the most-recently-used replacement algorithm and a simple clock replacement algorithm.
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Size: 316416 |
Author: david |
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Description: 用已知的空间两点求解声束穿过去界面的声束传播路径非线性算法。-Known spatial two o' clock solve the acoustic beam to pass through to the interface of the sound beam propagation path algorithm.
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Size: 1024 |
Author: zyc |
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Description: 在日常生活和工作中经常有人用到农历和公历的查询问题。因此，我借这次毕业设计之机，在辅导老师的指导下，编写了一个可以在VB6下正常运行的日历、计算器多功能应用程序，编程的思路是:先把公、农历的数据用数组查询设置好，再通过算法转换成具体应用。程序应用了不规则窗体技术，使得窗体比较美观。单击属相标志可以退出程序。单击时钟数字将返回到今天。单击查询控制面板开关将向下拉出查询控制面板。
-Query of the lunar calendar and the Gregorian calendar was often used in daily life and work. Therefore, I take this graduation design of the machine, written in VB6 under normal operation under the guidance of the counselors, calendar, calculator multifunctional applications, programming ideas: first public the Lunar' s data with the array query set by the algorithm to convert the specific application. The program application of irregular form, making the form more beautiful. Click Zodiac signs can exit the program. Click the clock numbers will return to today. Click the query will be down and out of the query control panel control panel switch.
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Size: 415744 |
Author: liuyan |
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Description: 主要仿真了基于物理层的时钟同步的仿真，耦合作用下，基于O.Simeone同步算法的处理过程，4个节点的时钟周期经过短暂的波动后逐渐达到稳定状态，实现了时钟偏差(skew)
的补偿，达成时钟频率的同步。-Major simulation clock synchronization based on physical layer simulation, coupling effect, based on O.Simeone synchronization algorithm process node four clock cycles after the short-term fluctuations gradually reached a steady state, the clock skew (skew) compensation reached clock frequency synchronization.
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Size: 1024 |
Author: 赵旋 |
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Description: 基于51单片机的12864曲线显示程序，本程序可扩展为显示时钟等曲线的算法。-51 microcontroller 12864 curve-based display program, the program can be expanded to display clock curve algorithm.
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Size: 40960 |
Author: 王晓鹏 |
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Description: 在VC开发环境下利用所提供的clock（）函数，实现先来先服务算法的模拟；可以用一个空循环或其他操作来模拟一个作业量，建议输入的作业量都在100－1000为宜。通过程序运行结果所显示的“作业号、作业量、提交时间、开始运行时间、执行时间、等待时间”的值来体现先来先服务原则。帮助学生加深了解作业调度的工作。-VC development environment using the supplied clock () function to achieve a first-come first-served algorithm simulation give an empty loop or other operations to simulate an amount of work, it is recommended that the amount of work input in 100-1000 is appropriate. The value shown by the result of the program, the job number, the amount of work, submit time, run time, execution time, waiting time " to reflect the principle of first come first served. To help students better understand the work of job scheduling.
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Size: 183296 |
Author: mrliu |
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Description: 操作系统 页面置换算法
设计和实现最佳置换算法、随机置换算法、
先进先出置换算法最近最久未使用置换算法、简单Clock置换算法及改进型Clock置换
算法-Operating system page replacement algorithm design and implementation of optimal replacement algorithm, random permutation algorithm, FIFO replacement algorithm is the most-recently-used replacement algorithm, a simple Clock replacement algorithm and improved Clock replacement algorithm
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Size: 2048 |
Author: |
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Description: java中时钟的使用，通过获取系统时间然后通过算法规范时间显示格式-java in the use of the clock by getting the system time and then by the algorithm specification time display format
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Size: 2048 |
Author: 唐宝 |
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Description: actelIP核 的fircore
Core Generator
– Executable File Outputs Run-Time Library (RTL)
Code and Testbench Based on Input Parameters
– Self-Checking – Executable Tests Generated
Output against Algorithm
• Distributed Arithmetic (DA) Algorithm
– Multiplier-Free Computation
– Low Cost
– Optimized for Actel FPGAs
• Folding Architecture to Minimize Design Size
– Serialized Computation when System Clock
Rate is Faster than the Data Sample Rate
• Efficient Structure Using Embedded RAMs
– Lookup Tables Utilize Embedded RAMs
• On-Chip DA Lookup Table Generator for FPGA
with Embedded RAMs
• Embedded RAMs Initialized as DA Lookup Table
• DA Lookup Table ROM Synthesis for FPGA without
Embedded RAMs
• Multiple DA lookup Tables to Split Large Number
of Taps
• Actel FPGA-Optimized RTL Code
• Supports 2 to 128 Taps
• 1- to 32-Bit Input Data and Coefficient Precision-actelIPcore fircore
Core Generator
– Executable File Outputs Run-Time Library (RTL)
Code and Testbench Based on Input Parameters
– Self-Checking – Executable Tests Generated
Output against Algorithm
• Distributed Arithmetic (DA) Algorithm
– Multiplier-Free Computation
– Low Cost
– Optimized for Actel FPGAs
• Folding Architecture to Minimize Design Size
– Serialized Computation when System Clock
Rate is Faster than the Data Sample Rate
• Efficient Structure Using Embedded RAMs
– Lookup Tables Utilize Embedded RAMs
• On-Chip DA Lookup Table Generator for FPGA
with Embedded RAMs
• Embedded RAMs Initialized as DA Lookup Table
• DA Lookup Table ROM Synthesis for FPGA without
Embedded RAMs
• Multiple DA lookup Tables to Split Large Number
of Taps
• Actel FPGA-Optimized RTL Code
• Supports 2 to 128 Taps
• 1- to 32-Bit Input Data and Coefficient Precision
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Size: 1051648 |
Author: 睿宸 |
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Description: 页面置换算法。实现最佳(Optimal)置换算法、先进先出(FIFO)置换算法、最近最久未使用(LRU)置换算法、简单Clock置换算法-Page replacement algorithm. Optimal (Optimal) replacement algorithm, FIFO (FIFO) replacement algorithm, the most recent time used (LRU) replacement algorithm, a simple replacement algorithm Clock
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Size: 316416 |
Author: 春春 |
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Description: 基于GPS的高精度时钟在线校频与授时研究.pdf,算法是基于最小二乘法的，同步精度达到-25-+25ns-Online GPS-based precision clock frequency and timing of the school, the algorithm is based on the least squares method, the synchronization accuracy reaches-25-+25 ns
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Size: 915456 |
Author: 沈宣佐 |
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Description: 操作系统页面替换算法，包括FIFO、OPT、LRU、CLOCK算法
-Operating system virtual page replacement algorithm, including FIFO, OPT, LRU, CLOCK. The four algorithm
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Size: 3072 |
Author: 江小五 |
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Description: 用MFC实现的模拟时钟程序，其中包括两个表盘，一个用走样直线实现，另一个用Wu反走样直线算法绘制指针-Analog clock with MFC program, including two dials, one implemented by aliasing line, another with Wu anti-aliased line drawing algorithm pointer
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Size: 2010112 |
Author: caoxin |
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Description: Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门 完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期 数据总线宽度可以是8-64位 支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联 握手协议，允许速率控制 可以达到每个时钟周期进行一次数据传输 支持普通周期结束、重试结束、错误结束等总线周期形式 支持用户自定义的标志:采用MASTER/SLAVE体系结构 支持多点进程(Multi-MASTER):仲裁算法用于定义 支持各种各样的IP核互联，包括USB、双向总线、复用器互联等 同步逻辑设计 非常简单的时序标准 与硬件实现技术无关(FPGA, ASIC等) 与设计工具无关。
相对于其他的IP核接口规范来说，Wishbone接口规范具有简单、开放、高效、利于实现等特点而且完全免费，并没有专利保护。基于上述优点，因此采用Wishbone总线进行接口设计。本文对Wishbone总线接口的设计参考了OpenCore上的有关设计。-
Wishbone specification has the following characteristics : a simple , compact, and requires very little logic gates complete common data bus data transfer protocols, including single reader , fast transmission, read-modify- write cycle, the event cycle data bus width can be 8-64 bit support big-endian (big-endian) and the small end (litle-endian), the interface automatically convert between the two. Support memory mapping , FIFO memory , cross interconnection handshake protocol that allows rate control every clock cycle to achieve a data transfer support normal cycle ends , retry the end , wrong end of the bus cycle and other forms support for user-defined flags : The MASTER/SLAVE architecture supports multi- process (Multi-MASTER): arbitration algorithm is used to define support a variety of IP cores interconnected , including USB, bi-directional bus , multiplexer interconnection , etc. synchronous logic design very simple timing standards technology-indepe
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Size: 12288 |
Author: 程浩武 |
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Description: 用Gardner算法时钟同步的BPSK的源程序-Gardner algorithm for clock synchronization with the source code BPSK
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Size: 1024 |
Author: 凝聚了 |
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Description: 基于matlab的128位aes加密解密算法 有效利用pipeline提高了设计的时钟频率和吞吐量 是一个十分高效的作品-Effective use of pipeline based on matlab 128 aes encryption and decryption algorithm improves the design of the clock frequency and throughput is a very efficient work
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Size: 17408 |
Author: tony |
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Description: 用Gardner算法时钟同步的BPSK的源程序-Gardner algorithm for clock synchronization with the source code BPSK
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Size: 1024 |
Author: rterwill |
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